WG – Cyril Seguin: SeeDep: Deploying Reproducible Application Topologies on Cloud Platform


Title: SeeDep: Deploying Reproducible Application Topologies on Cloud Platform

Speaker: Cyril Seguin (LIP, AVALON team)

Location: LIP, Salle du conseil du LIP 3rd floor

Schedule: 14:30


As part of the scientific method, any researcher should be able to reproduce the experimentation in order to not only verify the result but also evaluate and compare this experimentation with other approaches. The need of a standard tool allowing researchers to easily generate, share and reproduce experiments set-up arises. In this talk, I’ll present SeeDep, a framework aiming at being such a standard tool. By associating a generation key to a network experiment set-up, SeeDep allows for reproducing network experiments independently from the used infrastructure.

WG – Houmani Zeina: Study and design of data-driven services/microservices discovery mechanisms


Title: Study and design of data-driven services/microservices discovery mechanisms

Speaker: Houmani Zeina (LIP, Avalon team)

Location: LIP, council room 394 nord 3rd floor

Schedule: 14:30


— English version

Usual microservice discovery mechanisms are normally based on user needs (Goal-based Approaches). However, in today’s evolving architectures, several new microservices can be created. This makes the classic approach insufficient to discover the available microservices. That’s why customers need to discover the features they can benefit from before searching the available microservices in their domain. We will present a data-driven microservice architecture that allows customers to discover, from specific objects, the functionalities that can be exerted on these objects as well as all the microservices dedicated to them. This architecture, based on the main components of classic microservice architectures, adopts a particular communication strategy between clients and registers to achieve the desired objective.

— French version

Les mécanismes de découverte de microservices classiques sont normalement basés sur les besoins des utilisateurs (Goal-based Approches). Cependant, dans les architectures actuelles qui évoluent fréquemment, plusieurs nouveaux microservices peuvent être créés. Cela rend l’approche classique seule insuffisante pour découvrir les microservices disponibles. C’est pourquoi, les clients ont besoin de découvrir les fonctionnalités dont ils peuvent bénéficier avant de rechercher dans leur domaine les microservices disponibles. Nous allons présenter une architecture microservices pilotée par les données qui permet aux clients de découvrir, à partir d’objets spécifiques, les fonctionnalités qui peuvent être exercées sur ces objets ainsi que l’ensemble des microservices qui leur sont dédiés. Cette architecture, basée sur les composants principaux des architectures microservices classiques, adopte une stratégie de communication particulière entre les clients et les registres permettant d’atteindre l’objectif recherché.

WG – Mathieu Stoffel: Improving power-efficiency through fine-grain monitoring in HPC clusters


Title: Improving power-efficiency through fine-grain monitoring in HPC clusters

Speaker: Mathieu Stoffel (LIG, CORSE team)

Location: LIP, meeting room M7 3rd floor

Schedule: 14:30


Nowadays, power and energy consumption are of paramount importance. Further, reaching the Exascale target will not be possible in the short term without major breakthroughs in software and hardware technologies to meet power consumption constraints.
In this context, this papers discusses the design and implementation of a system-wide tool to monitor, analyze and control power/energy consumption in HPC clusters.
We developed a lightweight tool that relies on a fine-grain sampling of two CPU performance metrics: instructions throughput (IPC) and last level cache bandwidth.
Thanks to the information provided by these metrics about hardware resources’ activity, and using DVFS to control power/performance, we show that it is possible to achieve up to 16% energy savings at the cost of less than 3% performance degradation on real HPC applications.